1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
In a semiconductor memory device, a fuse element is provided to store redundancy address data when a defective memory cell is replaced by a redundant memory cell and the latter is then used, or control data for controlling the switch of voltage options for adjusting various voltage values used in an internal circuit.
Recently, there has been an increase in number of semiconductor memories which use storage elements similar in structure to memory cells for storing original data as such fuse elements. Especially, in the case of a nonvolatile memory such as a flash memory, a normal nonvolatile memory cell is directly used as a fuse cell.
A conventional semiconductor memory device equipped with such a fuse element, e.g., a mixed memory, is driven by two power sources, i.e., a 1.5V power source compatible to a CMOS logic, and a 3V power source for guaranteeing an analog circuit necessary to operate the semiconductor memory device. Because of the configuration of the two power sources, there are two detection circuits of 1.5V and 3V regarding a power-on detection circuit for detecting a voltage. Accordingly, when a fuse reading operation (chip initializing operation) is carried out, a power supply voltage level is determined by both detection circuits. Then, the fuse reading operation is started to read redundancy information of a chip stored in the fuse cell or information such as voltage trimming data.
For detection levels of the 3V and 1.5V power-on detection circuits, they must be designed not to exceed the lower limit VCCmin of a power supply voltage specification regardless of variance of the circuits. Furthermore, power-on detection levels must be designed to be higher than the operation lower limits of all circuits. Furthermore, since the memory device operates with two power supplies, it needs to be designed so that the circuits operate without problems under all considerable conditions for turning ON power supplies regardless of the turning ON order of the 1.5V and 3V power sources. For example, when data is read from the fuse cell, according to minimum power supply specifications of 1.5V, a fuse reading operation must be guaranteed at 0.8V considering 1.35V of the specifications, 1.25V at testing time, and a variance of 0.8 to 1.2V at the power-on detection circuit. When power supply specifications of 3V are in the range of 2.7V to 3.6V, considering a case in which a power supply voltage of 3V reaches sufficiently high 3.6V, fuse cell reading operations must be guaranteed under conditions of 0.8V in the case of 1.5V, and 3.6V in the case of 3V.
In reality, however, level changing from 0.8V to 3.6V which is larger by four times or more is difficult to achieve, and current balance of a 0.8V driving MOS transistor and a 3.6V driving MOS transistor is very lopsided even if it is achieved. An operation speed of a level changing circuit is consequently reduced. As the power-on circuit of a variance of 0.8V to 1.2V presumed here is 1.0±0.2V, it is not so large for the variance of the detection circuit. Thus, even if the power-on circuit of a small variance can be realized, VCCmin of the level changing circuit cannot be guaranteed, necessitating to guarantee the VCCmin of the level changing circuit by a conventional large-variance power-on circuit varied in the same direction as that of a variance of a transistor of the level changing circuit. As a result, the small-variance power-on detection circuit for guaranteeing fuse reading and the conventional large-variance power-on circuit are used together to guarantee VCCmin, constituting redundant circuitry. While the level changing circuit can be guaranteed by the conventional power-on detection circuit, it is difficult to set a sufficiently high level as it is a circuit of a large variance. For a redundant circuit, a margin of a VCCmin guarantee of the level changing circuit is small, and reliability is not so high. Further, as the level changing circuit is a circuit of the current of the MOS transistor, and the lower limit of the power supply voltage is different from that of the fuse reading circuit or the power-on detection circuit, circuit designing is difficult and, especially for examination of the fuse reading circuit, circuit designing is more difficult as there are two kinds of power supply voltages.